VECTOR PROCESSOR

摘要

PURPOSE:To prevent the deterioration of performance of a vector processor due to serializing control by adding a means to the vector processor to control the executing order of plural vector instruction elements. CONSTITUTION:When an advanced instruction is executed, a logic circuit produces a valid signal for execution of processing equivalent to a single vector element of the advanced instruction. The subsequent instruction is decoded while said valid signal is processed and therefore a writing counter 201 is cleared to zero. While the valid which executed the 2nd vector element of the advanced instruction is suppressed by a comparator 206. When the processing is through with the 1st element of the subsequent instruction, the valid signal is received through a bus 200 and the counter 201 is counted up. Thus the valid suppression is released and a reading counter 203 is counted up. Then an execution valid signal is obtained on a bus 209.