发明名称 |
CMOS memory arrangement with reduced data line compacitance |
摘要 |
A CMOS memory arrangement having each of a plurality of data lines connected to a plurality of bitlines, at least one of said datalines having a lesser number of bitlines in order to decrease capacitance in slower signal paths and thereby increase the operating speed of the memory. A multiple input sense amplifier is connected to the plurality of data lines.
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申请公布号 |
US4636988(A) |
申请公布日期 |
1987.01.13 |
申请号 |
US19850689254 |
申请日期 |
1985.01.07 |
申请人 |
THOMSON COMPONENTS-MOSTEK CORPORATION |
发明人 |
TRAN, HIEP V. |
分类号 |
G11C7/10;G11C7/18;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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