发明名称
摘要 PURPOSE:To enable formation of the drain layer on the circumference of the V groove aperture section with a narrow width and also to increase the degree of integration for the subject semiconductor device by a method wherein side etching is performed for the master pattern to be used for the formation of the V groove and then impurities are lead in. CONSTITUTION:A P<+> Si layer 2 and a P<-> Si layer 3 are formed successively, and an SiO2 film 4, and an Si3N4 film 5 are deposited. A V groove mask pattern 7 and an electrode window mask pattern 8 are formed using a photolithographical technique, then a P channel cut layer 12 and a separating layer 13 are formed. The Si3N4 film 5, exposed to three directions of end face, is side-etched and a groove matched pattern 14 is formed. Then drain layers 16, 16' and an SiO2 film 17 are formed by an ion injection and the like, and the V groove matched pattern 14 is removed and a V groove 20 is formed. As a result, the drain layer 16 having a narrow width can be formed on the circumference of the V groove 20.
申请公布号 JPS621267(B2) 申请公布日期 1987.01.12
申请号 JP19790164988 申请日期 1979.12.19
申请人 FUJITSU LTD 发明人 MATSUMOTO TAKASHI;WADA KUNIHIKO;OGAWA TSUTOMU;SASAKI NOBUO
分类号 H01L29/78;H01L21/336;H01L29/08;H01L29/417 主分类号 H01L29/78
代理机构 代理人
主权项
地址