| 摘要 |
PURPOSE:To improve the extent of integrating of a device, by providing, in wiring regions provided between basic cells, diffused regions connected to the well potential of the basic cell and to the substrate potential source. CONSTITUTION:A plurality of basic cells 200A each consisting of two MOS transistors are provided on a semiconductor substrate so as to form cell arrays. Wiring regions 7 and 17 for providing logic circuits in future processes are provided between the cells. An N<+> type diffused region 8 and a P<+> type diffused region 18 are provided in these wiring regions 7 and 17, respectively, and they are connected to the well potential of the basic cell and the substrate potential source. It is thereby enabled to decrease the width of the basic cell 200A to the distance defined between wires 16 with polycide structure and thus to decrease the size of the basic cell. Accordingly, the extent of integration of the device can be improved. |
