| 摘要 |
<p>PURPOSE:To prevent erroneous data from being written in a column latch by changing the time of a logic '0' by a writing enable signal and informing the completion of the first cycle. CONSTITUTION:From when respective chip and write angle signals the inverse of CE and the inverse of WE become both a logic '0', the first cycle is started and by the faster rise, the writing to a column 1 is executed. The time width to some extent larger than the regular pulse width of the the inverse of WE is set as (w), the time lapse is supervised from the fall point of the inverse of W, when the inverse of WE rises within the width (w), this is recognized as the writing control signal of the first cycle, and at the rise point of the inverse of W, the data of an input buffer 5 are written to the latch 1. On the other hand, when the inverse of WE does not rise at the time point within the width (w), this is recognized as the starting indicating signal of the second cycle, by the rise of the inverse of WE after the width (w) passes, the external writable signal is set to the logic '0', and the second cycle is started.</p> |
