| 摘要 |
<p>PURPOSE:To prevent erroneous action by informing and controlling the border time point of the first and second respective cycles from an external circuit in the relation of the pulse width of respective write and chip enable signals. CONSTITUTION:From when respective chip and write enable signals the inverse of CE and the inverse of WE are both a logic '0', the first cycle is started, and by the faster risen signal out of these, writing is executed from an input buffer 5 to a column latch 1. The fall point of the inverse of WE is detected to be earlier than the fall point of the inverse of CE, and at the rise point of the inverse of CE, the inverse of WE is a logic 0. Then, at the rise point of the inverse of CE, the external writable signal is set to the logic '0' and the first cycle is completed. Thereafter, a memory cell array 7 recognizes that the prescribed assembly of the inverse of WE and the inverse of CE is the notice of the cycle converting point, and is shifted to the second cycle at the rise point of the inverse of WE.</p> |
