发明名称 Integrated digital circuit for logarithmic signal processing
摘要 An integrated circuit for logarithmic signal processing has a logarithmic converter and a logarithmic computer, each with a comparator array logic (CAL circuit). The CAL circuit has a large number of comparators, which are connected to each other, and are arranged in an array. A digital value is stored in each of the comparators. The CAL circuit stores all digital values in monotonically ascending or descending sequence. Each of the comparators receives the input data signal and compares it with the digital values which are stored in the comparator. A comparison signal which depends on the comparison is generated. The comparison signal of every comparator is received by an end cell, which also receives the comparison signal of the immediately adjacent comparator. The end cell generates an output signal. An end cell is assigned to each comparator. The large number of output signals from the end cells gives the position of the comparator of which the stored digital value is next to the value of the input data signal. <IMAGE>
申请公布号 DE3622205(A1) 申请公布日期 1987.01.08
申请号 DE19863622205 申请日期 1986.07.02
申请人 VLSI TECHNOLOGY,INC. 发明人 FULTON WAGNER,LAWRENCE;PETER BURLESON,WAYNE;PHILIP GUADAGNA,JOHN;VAN DYKE,KORBIN S.;DONALD HEMMING,ROBERT
分类号 G06F1/03;H03M7/24;(IPC1-7):G06F7/38 主分类号 G06F1/03
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