| 摘要 |
A PLL frequency synthesizer includes a VCO (1) for generating an oscillation of a frequency varying in response to a control voltage, a variable frequency divider (2) for dividing the output frequency of said VCO in a ratio according to a control signal, a reference oscillator (5) for supplying a reference signal having a predetermined frequency, a fixed frequency divider (4) for dividing the frequency of said reference signal in a fixed ratio, a phase comparator (3) for comparing the phases of the outputs of said fixed frequency divider to provide a control pulse corresponding to a phase difference between these outputs, a charge pump (16) having a power supply terminal for generating a charge/discharge voltage in response to said control pulse, a loop filter (7) including a capacitor (72) supplied with said charge/discharge voltage for supplying to said VCO as said control voltage a voltage corresponding to said charge/discharge voltage, and a power supply circuit (10) responsive to the output of said fixed frequency divider and supplying said boosted DC voltage (VH) to said power supply terminal. |
