SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE:To prevent wrong data from being written in a column latch at the end of the 1st cycle of an EEPROM, where page mode writing is executed, by informing a semiconductor memory device of the termination of the 1st cycle by another signal transmission method without a timer. CONSTITUTION:Since a conventional device does not always synchronize with external signals, such as the inverse of CE and the inverse of WE at the rise point of a timer output, right data may not be written in the column latch 1 when the inverse of CE and the inverse of WE are both of logic '0' and the timer output, trails, so that, an external writable signal trails, while data is written in the column latch 1. This invention sets the inverse of WE at logic '0' during a certain period while the inverse of CE is held at logic '1' after an external circuit recognizes that the right data Dn is written at an address position shown by An due to the leading of the inverse of WE. Because of the rise of the inverse of WE, the external writable signal trails. The combination of signals where the inverse of WE comes to logic '0' during a certain period as the inverse of CE is held at logic '1' cannot be available under other conditions.