| 摘要 |
<p>A semiconductor memory (DRAM) device comprises memory cells, each of which is composed of an FET (4s, 4c, 4d, 5,6) and a capacitor. The FET has a SOI structure. The capacitor has its dielectric layer (3b) formed by the insulating layer of the SOI structure, an upper capacitor electrode formed by the semiconductor layer (4) of the SOI structure, and a lower electrode formed by the semiconductor substrate (1). This enables the substrate to be biased with a voltage at an intermediate level between a first storage voltage and a secnd storage voltage.</p> |
