发明名称 |
Detection and correction of multi-chip synchronization errors |
摘要 |
A uniprocessor if formed on plural independently controlled chips each including a primary instruction driven controller and a secondary error driven self-sequencing controller. Each instruction is supplied in parallel to each primary controller which generates an EXIT signal, as it completes execution, to a common external EXIT line. Hardware monitors the local EXIT signal and the common EXIT line state and activates the secondary controller, when a mismatch is detected, to set an on-chip reset predominant error latch driving a common external ERROR line, an ERROR-state on which also sets the latches and activates any inactive secondary controller to drive its chip to a first predetermined state and to reset its latch. When no ERROR signal remains, the secondary controllers cycle in synchronism through an ERROR routine, exiting to instruction control.
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申请公布号 |
US4635186(A) |
申请公布日期 |
1987.01.06 |
申请号 |
US19830506488 |
申请日期 |
1983.06.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
OMAN, PRICE W.;RINALDI, MARK A.;RUSSO, VITO W.;SALYER, GREGORY |
分类号 |
G06F9/38;G06F9/22;G06F9/28;G06F13/42;(IPC1-7):G06F11/00;G06F13/00 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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