发明名称 ARITHMETIC LOGICAL UNIT AND ITS DRIVING METHOD
摘要 PURPOSE:To operate the absolute value of a difference between two signals at a high speed only by one instruction by providing the titled unit with an arithmetic logical circuit for executing the logical operation and addition/ subtraction of two input signals, a subtractor for executing prescribed subtraction and a selecting circuit for selecting the outputs of both the circuits. CONSTITUTION:Input signals A, B are inputted from input signal lines 11, 12 respectively. When an absolute value arithmetic mode is determined by an instruction signal line 13, an arithmetic logical block 1 is set up to a subtraction mode and a difference A-B is outputted to a signal line 14. On the other hand, a difference B-A is outputted to an output side signal line 15 of the subtractor 2. The selecting circuit 3 executes the following operation. At first, the code of the subtracted result A-B outputted to the signal line 14 is decided. In case of 2's complement display, a maximum bit '0' shows a positive and a maximum bit '1' shows a negative. The maximum bit is decided and the signal A-B or B-A is outputted to an output signal line 16 in case of '0' or '1' respectively. Namely, when the A-B is a positive, an output D becomes A-B, and in case of a negative, B-A is outputted. Since ¦A-B¦=¦B-A¦, a positive value, i.e. ¦A-B¦, is always outputted to the output D.
申请公布号 JPS61296427(A) 申请公布日期 1986.12.27
申请号 JP19850138822 申请日期 1985.06.25
申请人 NEC CORP 发明人 YASUMOTO MASAAKI;ENOMOTO TADAYOSHI
分类号 G06F7/00;G06F7/38;G06F7/50;G06F7/505;G06F7/57 主分类号 G06F7/00
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