| 摘要 |
PURPOSE:To keep always the phase locked range of a phase locked loop PLL to a constant range even when the control voltage of a voltage controlled oscillator VCO is changed due to external disturbance by applying negative feedback to the control input change of the VCO so as to keep the difference in the control voltage of the VCO equal. CONSTITUTION:A sample and hold circuit 8 is provided, which samples and holds the DC level of an output signal (d) of a PD 2 and feeds back the result to a terminal (e) of a diode. Then the DC level of the output signal (d) of the PD 2 and the DC level at the terminal (e) are changed in-phase. The difference between a control voltage in a high level frequency FH and a control voltage in a low level frequency FL is kept equal against the control voltage in the free run frequency FM and the range of the lock range of the PLL is kept always constant against the temperature change. |
