| 摘要 |
PURPOSE:To constitute a circuit used even with a slow leading of a power supply in the inside of a chip without using external terminals by using a MOS transistor (TR) whose gate and drain are connected as a load connected between a capacitor and a power terminal in an integration circuit. CONSTITUTION:Two PMOS TRs Q2, Q3 connected in series between the power terminal Vdd and one terminal of a capacitor C. The gate and drain of the TRs Q2, Q3 are connected and the other terminal of the capacitor C is connected to a common terminal. The TRs Q2, Q3 and the capacitor C are all formed on an integrated circuit chip to constitute an integration circuit. The output of the integration circuit is inputted to an inverter G1 as a buffer circuit and the output signal of the inverter G1 is a reset signal. Since the integration circuit of a power-on reset circuit utilizes an on-resistance of the MOS TR the integration circuit is not activated when the power voltage Vdd is not the sum or over of the threshold values of the TRs Q2, Q3 connected in series.
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