发明名称 METHOD FOR ETCHING SILICON
摘要 PURPOSE:To ensure enable etching for a very small place on the surface of a p-layer by a method wherein a silicon wafer equipped with a p-n junction is placed in an alkaline liquid and a pulsating voltage is repeatedly applied across the p-layer and n-layer of the silicon wafer or across the silicon wafer and the alkaline liquid. CONSTITUTION:A pulsating voltage source 10 applies a pulsating voltage to a silicon wafer 3. The silicon wafer 3 is constituted of a p-layer 3a and an n-layer 12 covering the p-layer 3a with very small portions 11a, 11b left exposed. When the pulsating voltage source 10 applies a voltage of 5V pulsating at 0.04Hz to the n-layer 12, the entry/exit of ions is obstructed to lower the etching rate, because a barrier emerges in the small portions 11a, 11b belonging to the p-layer 3a when the n-layer 12 is exposed to a voltage of 5V. When the voltage is zero at the n-layer 12, there exists no barrier and the entry/exit of ions is freely made, which allows the very small portions 11a, 11b to be effectively affected by etching.
申请公布号 JPS61295636(A) 申请公布日期 1986.12.26
申请号 JP19850138592 申请日期 1985.06.25
申请人 YOKOGAWA ELECTRIC CORP 发明人 IKEDA KYOICHI;WATANABE TETSUYA
分类号 H01L21/3063;H01L21/306 主分类号 H01L21/3063
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