| 摘要 |
<p>PURPOSE:To perform high-speed operation by simple constitution with low power consumption by dividing precharged signal lines into two parts, i.e. part to which a TR for a decoder is connected and other parts by using an n channel MOSTR and arranging a p channel MOSTRs at each part. CONSTITUTION:When a clock signal phi is at H, an n channel MOSTR NT1 is on and a p channel MOSTR PT3 is off, thereby outputting an output signal Vout corresponding to an address signal ADi. In a precharge period wherein the signal phi falls to L, the NT1 turns off, nodes A and A' are separated electrically, and respective signal lines are precharged by the PT1 and PT3. At this time, a node A' is separated electrically from the node A, so there is no influence of n channel MOSTRs T1-Tn upon parasitic capacity, so that signal lines are precharged at a high speed. An input to an inverter I responds to the signal phi at a high speed in combination with the effect of PT2 and the power consumption also decreases.</p> |
