| 摘要 |
PURPOSE:To reduce the resistance value of an N<-> layer, by forming a low-concentration impurity diffused layer having a reverse conducting type with respect to a semiconductor substrate at a lower part of a side wall on one side, and forming a high- concentration impurity diffused layer having the same impurity as that in the low- concentration diffused layer at a lower part of a side wall on the source side. CONSTITUTION:On a P-type 100 substrate 1, a gate oxide film 2 is formed. A polysilicon film is formed. Phosphorus is doped by thermal diffusion. Then, with a photoresist film 7 as a mask, anisotropic etching is performed. Thus a gate electrode 3, whose side surface is approximately vertical is formed. With the gate electrode 3 as a mask, phosphorus is implanted in the silicon substrate at a slant angle of about 10 deg. to the drain side. The phosphorus-ion implanted layer is formed so that the layer is separated from the end part of the gate electrode. An oxide film 4' is formed by a plasma CVD method. Thereafter, anisotropic etching is performed until the surface of the silicon substrate 1 is exposed, and a side wall 4 is formed. Arsenic is implanted at a slant angle of about 10 deg. to the source side, which is opposite with respect to the phosphorus-ion implanting direction. Thus, the arsenic-ion implanted layer is formed. Therefore, suppression of a hot carrier effect and the suppression of increase in channel resistance can be simultaneously realized.
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