| 摘要 |
PURPOSE:To improve the application efficiency of hardware by using a mode signal which prescribes the number of elements to which simultaneous accesses are possible to correct the difference between the address information on the final element of the 1st data and that on the head element of the 2nd data. CONSTITUTION:An adder circuit 1 calculates the bank address of the final element of data and supplies it to a register 2. A subtractor circuit 3 uses a mode signal which prescribes the number of elements to which simultaneous accesses are possible to calculate the difference between the bank address of the final element and that of the head element of data given from the register 2 and supplies the obtained difference to a gate circuit 4. a shift circuit 5 supplies the difference of bank addresses masked by the circuit 4 to a subtractor circuit 6 after shifting it. The circuit 6 subtracts the difference between the shifted bank addresses from the information on the memory bank cycle time and supplies the result of subtraction to a gate circuit 7. Then the waiting cycle number is led out of the circuit 7. |
