| 摘要 |
PURPOSE:To reduce the power consumption of an IC by supplying a positive feedback signal from the 2nd load FET parallel to a load MOSFET to a logical gate consisting of the 1st load MOSFET which is driven with a one-shot pulse signal generated at operation timing and a driving MOSFET. CONSTITUTION:Plural memories consisting of a MOSFET element Qm for address selection and a capacitor Cs for information storage are coupled regularly with a couple of complementary data lines D and D' which are arranged in parallel, and a switch MOSFET element Q5 provided between data lines D and D' constitution a precharging circuit PC to put a RAM in an operation state through the amplifying operation of a sense amplifier SA. Thus, the data lines D and D' are controlled to a high or low level to reduce the power consumption of the IC including a decoder circuit and also lower a noise level generated owing to capacitive coupling.
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