发明名称 BUFFERED DELAY LINE
摘要 PURPOSE:To reduce the input resistance of an LC delay line by selecting a capacitance of a capacitor and an inductance of a coil so as to cause a specific relation. CONSTITUTION:No input resistance is inserted between an input inverter 5 and an LC delay line 4 in the buffered delay line. In order to eliminate the need for an input resistor between the input inverter 5 and the LC delay line, the capacitance C of the capacitor 2 and the inductance L of the coil 3 constituting each constant K-type low pass filter 1 are selected so as to form respectively C=td/r and L=td.r, where (r) is an output resistance of the input inverter 5 and td is the required inter-tap delay time td. Thus, the circuit is matched without inserting any input resistor between the input inverter 5 and the LC delay line 4.
申请公布号 JPS61294917(A) 申请公布日期 1986.12.25
申请号 JP19850136528 申请日期 1985.06.21
申请人 MURATA MFG CO LTD 发明人 HATA TOSHIO;YONEZAWA MASAO
分类号 H03H7/32 主分类号 H03H7/32
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