| 摘要 |
PURPOSE:To make circuit constitution simple and easy and to keep the generation of a reset release signal constant by constituting the titled circuit of a AND gate or a OR circuit and two resistors only. CONSTITUTION:In applying power, a voltage at a reset signal output terminal 6 is equal to a power voltage level (logical value '1') via a resistor 4 and a flip-flop or the like in an integrated circuit is reset. In such a case, two inputs are at logical '1' and a AND ate circuit 5 keeps to output a reset signal. A clock signal is fed to a clock pulse input terminal 1 and a clock pulse goes to a common level, that is, logical '0', then an output of the AND gate circuit 5 goes to a common level, a reset release signal is outputted from a reset signal output terminal 6 to release the reset of the flip-flop or the like in the integrated circuit. Thus, the AND gate 5 keeps outputting the reset release signal independently of the inputted clock pulse.
|
