| 摘要 |
PURPOSE:To prevent the reduction in processing capability of a host processor and the delay in response time by constituting the titled controller of a reception buffer, a transmission buffer, a switchboard interface circuit, a switchboard state memory and a processor having switchboard monitor and control functions. CONSTITUTION:The switchboard controller PCTL1 is provided with information transmission functions between a host processor including a main storage device and plural switch boards POSo30-POSm3m and pattern display functions displaying the pattern of a desired switchboard by the key operation of the operator. The PCTL1 consists of a reception buffer R10, a transmission buffer S11, a switchboard interface circuit I12 transmitting/receiving information to/ from each of the POSo30-POSm3m, a switchboard state memory PM13 stores in the information displayed on each pattern of the POSo30-POSm3m and the state of lighting/extinguishing of a lamp and a processor 14 controlling the R10, S11, I12 and PM13 and identifying the switchboard monitor.
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