| 摘要 |
PURPOSE:To enable the display of the hourly generation sequence of data sampled by individual sampling systems, by arranging a clock decision circuit, a memory, an address counter and the like. CONSTITUTION:A sampling system 11A and a sampling system 11B are operated by an internal clock 5. On the other hand, the output of a clock decision circuit 1E enters a memory 12 as decision signal 1F while the output of a clock decision circuit 2E, and the memory 12 as decision signal 2F. Then, when the decision signal 1F or 2F comes up, the identification of the data, from which sampling system it is sampled is memorized at respective addresses of the memory 12 while the counter 13 is incremented to update the address of the memory 12. Thus, the hourly sequential relationship can be found about the input data 3A memorized in the sampling system 11A and the input data 3B memorized in the sampling system 11B from the memory 12 and the counter 13. |
