| 摘要 |
PURPOSE:To generate a disturbance signal efficiently and with a better reducibility with a minimum resolution of a test signal generation circuit, by adding up the output of a timing register and the output of a constant register with an adder. CONSTITUTION:In a timing register 9, a timing value is set with a controller 10 prior to a test. A selector 11 selects one of outputs 13 of the register 6 and an adder 12 and the data selected is connected to one input of the adder 12 while the output 15 of a constant register 14 done to the other input of the adder 12. The contents of the register 14 is set with the controller 10. Then, the output 13 of the adder 12 is connected to a timing generation circuit 16 and a clock generator 17 generates the start edge of the clock on the basis of the output of the circuit 16. |
