发明名称 FACILITATING CIRCUIT FOR ON-CHIP MEMORY TEST
摘要 PURPOSE:To make it possible to perform a test even in a finished product and to completely test the operation of a memory cell in a short period by writing the same data at plural memory cells and comparing the data read out with the data written. CONSTITUTION:On the test, switches SW1 and SW2 are turned on and a switch SW3 is turned off by the output of a test control circuit 21 and the same test input data is written on four memory cells out of a memory cell array 14 from a data input terminal 11 through an input buffer 12 and input/output circuits 131-134. The test input data written on the four memory cells are simultaneously read out and are supplied to an AND circuit 16 and an OR circuit 17. A comparison between AND data and OR data outputted from data output terminal 18 and 19 and the test input data is performed and only when all of them are equal, it is judged that the four memories are correctly operated.
申请公布号 JPS61292299(A) 申请公布日期 1986.12.23
申请号 JP19850132596 申请日期 1985.06.18
申请人 TOSHIBA CORP 发明人 FURUYAMA TORU;OSAWA TAKASHI
分类号 G06F11/22;G11C11/401;G11C29/00;G11C29/34 主分类号 G06F11/22
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