TIMING SIGNAL GENERATING CIRCUIT

摘要

PURPOSE:To generate a timing signal at an optional time axis within a basic period, that is, at an optional phase by varying variable delay information in various ways. CONSTITUTION:A delay selector 143 generates a timing signals E4 having a prescribed delay period (T+DELTAT4) by selecting an output of a delay element producing a delay output DELTAT4 from delay elements 1411-141m of a shift register 141 according to the variable delay information DELTAT4 inputted from a latch circuit 142. Similarly, the next timing signal E5 is generated. In selecting the basic period to the timing signal E5 as T4 (T5=T4) and the variable delay information T5 as zero, the period of the timing signal E5 is (T4-DELTAT4). Thus, the minimum period Tmin limited by a delay time Tpd existing in the timing period designation circuit 120 is selected as the basic period T4 and the value DELTAT4 is changed variously to generate a timing signal having a shorter period than the period Tmin.