发明名称 ECL-TTL CONVERTING AND OUTPUTTING CIRCUIT
摘要 PURPOSE:To shorten the delay time from the switching of an input t variation in output voltage by driving transistors (TR) of an output stage with a TTL output voltage through a capacitor. CONSTITUTION:When the output of an ECL circuit is supplied from input terminals 11 and 12, a TTL output is obtained from the collectors of TRs4 and 5 constituting a differential amplifier. This TTL output turns on and off TRs1 and 2. The base of the TR1 and the collector of the TR4 are coupled together through the capacitor 22. Consequently, capacities between the collector and base, and base and emitter of the TR1 are charged or discharged abruptly in a transient state wherein an output voltage rises or falls. Therefore, the delay time from the switching of the input voltage to the variation in output voltage is shortened.
申请公布号 JPS61293022(A) 申请公布日期 1986.12.23
申请号 JP19850134856 申请日期 1985.06.20
申请人 SONY CORP 发明人 SHOJI NORIO;TAKEDA HITOSHI
分类号 H03K19/013;H03K19/018 主分类号 H03K19/013
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