| 摘要 |
PURPOSE:To improve bus using efficiency by converting the conversion function of a data width into a hardware by making use of the control signal of an FIFO memory. CONSTITUTION:The data are delivered onto a bus 11 of 16 bits and a transfer request signal 21 is supplied from outside. Thus a control circuit 2 delivers a latch strobe signal 31 and latches the 16-bit data via a latch 4. Then the circuit 2 delivers a control signal 32 for selection of data equivalent to 8 bits delivered onto an 8-bit bus 12 and sends an input request signal 22 for the 8-bit data delivered onto the bus 12 to an FIFO memory 1. While the 8-bit data selected by a multiplexer 3 among those 16-bit data latched by the latch 4 are delivered onto the bus 12. The memory 1 supplies the 8-bit data on the bus 12 according to the signal 22 and then sends an input end signal 23 to the circuit 2. The circuit 2 detects the signal 23 and switches the 8-bit data selected by the multiplexer 3.
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