| 摘要 |
PURPOSE:To shorten the instruction executing time by inhibiting the repetition of the memory access and arithmetic operation to the same address when two operands overlap completely with each other in a pipeline information processor. CONSTITUTION:When two operands are completely coincident with each other, the start and end addresses of both the 1st and 2nd operands are stored successively into address registers A-D. Then a comparator 3 and an overlap detecting circuit 4 confirm the coincidence between both operands. Thus an indication for discontinuation of operand supply is reported to an address generation control part 5 and an arithmetic control part 6 via signal lines 16 and 17 respectively. Thus the part 6 delivers immediately its arithmetic result as an instruction result when said indication is received and at the same time informs the start of the next instruction to the part 5.
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