Data processing system capable of transferring single-byte and double-byte data under DMA control

摘要

A data processing system having a data bus with a two-byte capacity provides for the DMA transfer of both one-byte data and two-byte data between a memory and an input/output adapter. An address counter and a byte counter receive a start address and a byte number indicating the number of bytes to be transferred, respectively, through the system bus from the processor. The least significant bits in the start address and the byte number are used to control whether the data transfer on the bus will be a one-byte transfer or a two-byte transfer for the first transfer operation and the last transfer operation.