| 摘要 |
PURPOSE:To attain the detection of consecutive zeros without causing mis- conversion by providing two memories to the pre-stage of a multiplex circuit in a buffer memory converting '0' into '1' for preventing consecutive zeros. CONSTITUTION:A data Dn is generated by an information generation circuit 11, stored in memories 13, 14 at first and a consecutive-zero detection circuit 15 detects consecutive zeros at the same time. When no consecutive zero is detected, the data Dn in the memory 14 is sent directly. When the circuit 11 generates a data Dn+1 next, the data is written in both the memories and if consecutive zero is detected, a clock to the circuit 11 is stopped and a selector 12 is thrown to the position of the memory 13. The circuit 15 sends a read signal to the memory 14 to send only a data D'n+1 except a part X overflowed by the insertion of '1' to a multiplex circuit 16. The circuit 16 inserts '1' to the data D'n+1 and sends the result. The memory 13, the same as the memory 14, reads only the frame X overflowed and inputs the result to the selector 12. Thus, the said X is added to new data Dn+2 of both the memories and used for the detection of consecutive zero.
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