| 摘要 |
PURPOSE:To prevent hazard from occurring even when an input has a skew to some extent by adding two delay elements and four two-input logical circuits. CONSTITUTION:A signal from a terminal 11 is supplied to one input of a NOR gate NO11 and one input of a NAND gate NA22 through an inverter I11 and a delay element 21. Further, it is supplied to the other-input sides of gates NO1 and NA22 through the inverter I11. Similarly, a signal from a terminal 12 is supplied to NOR gates NO13 and NA24. Consequently, waveforms of nodes 13-16 are as shown by C-F and waveforms at output terminals 17-20 are as shown by G-J. Therefore, the signals from the terminals 11 and 12 have a skew of DELTAt1, no hazard is caused in the signals at 17-20 when the skew of DELTAt1 is smaller than the delay time DELTAt2 of delay elements 21 and 22.
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