| 摘要 |
PURPOSE:To shorten an access time even with no use of a cache memory by applying advance reading to the 2nd and subsequent continuous instruction fetching accesses. CONSTITUTION:When a detection circuit 104 detects the continuous instruction fetching accesses, the circuit 104 outputs the continuous instruction fetching signals 116. By the operation of signal 116, a timing generating circuit 105, an address latch 106, an address adder 107 and a data latch 108 operate so as to transmit the data read out in the latter half of the immediately preceding instruction latch access to a CPU 101. Thus the CPU 101 can fetch data just in the data fetch time of its own since the memory access time utilizes the latter half of the immediately preceding instruction fetch access.
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