| 摘要 |
PURPOSE:To simplify the constitution of a circuit, to decrease the hardware quantity, and to realize synthetically the economization by providing a signal line for a time slot, separately from that for a channel for voice, and also discributing a common clock to each unit. CONSTITUTION:A PCM signal of 2.048Mb/s from outgoing highways 4a (4b) is multiplexed by a 4 highway portion by MPXs 5a (5b), converted to 8.192Mb/s, 128 time slots, and 120 channels, and thereafter, sent out to a unit of the other party side through a cable driver 13a. PGs 6a (6b) count '0' and '1' of a passing signal bit, and insert a parity signal into a time slot '0' (or a time slot 16) being an idle time slot. On the other hand, a signaling bit which is sent from CPs 2a (2b) is accumulated temporarily in a buffer memory of SSMs 7a (7b) through CTLs 8a (8b), formed to the same multiplicity as a voice channel, and sent out to the unit of the other party side through cable drivers 13a (13b) by a timing of the CTLs 8a (8b).
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