发明名称 TEST INSTRUCTION PROCESSING SYSTEM
摘要 PURPOSE:To simplify a circuit, and to make a device small in size by using a shifter circuit in common with a processing circuit of a test instruction. CONSTITUTION:A data to be inspected 1 of an operand of a program to be tested is read to a test instruction processing circuit 3 and processed by a test instruction 2. The processing circuit 3 is constituted of a bit extracting circuit 4 for extracting a bit of the data to be inspected 1 designated by the test instruction 2, a shifter 5, and a testing circuit 6 for testing the extracted bit. The extracting circuit 4 is connected to the shifter circuit 5 in order to extract a necessary bit of the data to be inspected 1, and the bit which is extracted by the shifter circuit 5 outputs a test result 8 through the testing circuit 6 for executing a test of its bit. The shifter circuit 5 is used in common with other data processing, therefore, a data for showing its shift quantity, and an input data are switched by a gate 7, and the constitution of the circuit can be simplified.
申请公布号 JPS61290531(A) 申请公布日期 1986.12.20
申请号 JP19850134980 申请日期 1985.06.19
申请人 FUJITSU LTD 发明人 AKASAKA TSUTOMU;TSUJITA HIROYUKI
分类号 G06F7/00;G06F7/76;G06F9/30;G06F9/308 主分类号 G06F7/00
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