| 摘要 |
PURPOSE:To improve the efficiencies of a diagnosis and a test by generating a spurious error in an optional place by synchronizing with the execution of the processing of a data processor. CONSTITUTION:When a data processor is operated, an instruction decoder 3 analyzer a macro-instruction, and sets a control storage CS address to a CS address register (CS ADRR) 4. A scan-in (SCI) start CS ADR comparing circuit 13 compares the contents of the CS ADRR 4 with the contents of an SCI start CS ADRR 11, and sends out a start control signal if the addresses coincide with each other. An SCI end CS ADR comparing circuit 14 compares the contents of the CS ADRR 4 with an SC end CS ADRR 12, and sends out an end control signal if the addresses coincide with each other. An SCI controlling circuit 22 makes an error generating circuit 23 instruct the start of an SCI to the SCI ADR position of an SCI ADRR 21, by a start control signal from the comparing circuit 13, and executes a control so that the SCI is ended by an end control signal from the comparing circuit 14. |
