发明名称 ERROR DETECTING AND CORRECTING SYSTEM
摘要 PURPOSE:To detect the generation of a hardware of an error detecting and correcting circuit by obtaining a check bit by using one unit of a divided data train at least two times each, and comparing one unit data by an exclusive OR circuit. CONSTITUTION:An inspection is executed to a data string, a check bit is added and stored in a storage device, a new inspection is executed to the data train provided with the check bit, which is read out of the storage device, except the check bit, and the check bit is obtained and compared with the check bit which is read out. In such a way, an error detecting system of an information processing system which has provided an error detecting and correcting circuit which can execute an error correction of 1 bit and error detection of 2 bits, with regard to the data string, on a CPU and the storage device is formed. The check bit is obtained by using one unit of the divided data train at least two times each. Also, by comparing the one unit data with each other by an exclusive OR circuit, the calculation for detecting the generation of a hardware error in case of detecting and correcting an error is executed.
申请公布号 JPS61290541(A) 申请公布日期 1986.12.20
申请号 JP19850133184 申请日期 1985.06.19
申请人 FUJITSU LTD 发明人 SUGIURA SADANARI
分类号 G06F11/10 主分类号 G06F11/10
代理机构 代理人
主权项
地址