发明名称 MEMORY ACCESS CONTROL SYSTEM
摘要 PURPOSE:To shorten a processing time for checking the existence of a memory request and to execute rapidly and efficiently memory access by expanding/ contracting the number of time divisions to check the existence of the generation of each memory access request signal in accordance with the generating state of the memory access request signal. CONSTITUTION:Processing is executed always by the number of time divisions to receive only a memory access request having the highest generation frequency, and if another memory access request is generated, the processing is executed by an expanded time divisions number to receive all memory access requests having the generation frequency more than that of said memory access request. Namely, a decoder 1 inputs memory access request signals 1A-1F and outputs a specific value to a counter 2 in accordance with the existence of these request signals. The counter 2 outputs the value loaded from the decoder 1 to a decoder 3. The counter 2 executes the increment operation of the output value at clock 100 (corresponding to time division frequency).
申请公布号 JPS61289437(A) 申请公布日期 1986.12.19
申请号 JP19850130835 申请日期 1985.06.18
申请人 TOSHIBA CORP 发明人 SASAKI MASANARI
分类号 G06F12/00;G11C7/00 主分类号 G06F12/00
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