| 摘要 |
PURPOSE:To realize a master slice type semiconductor device consuming less electric power in its static operation by a method wherein a P-type and N-type FETs comprise a memory cell and an end of the FETs is connected to a bit line, the other end thereof to an end of the power source, and the gate thereof to a word line. CONSTITUTION:An address decoder 24 selects one out of word lines 22, and a word line 221 is used to place the memory cell of an N-type transistor 26 in the ON state. Simultaneously, a word line 222 place the memory cell of a P-type transistor 25 in the ON state, for the read of data respectively into the corresponding bit lines 21. That is to say, a P-type transistor and N-type transistor that are the basic logical elements of a CMOS gate array are used as a memory cell. To memorize data, the sources are respectively connected to VSS ('0') and VDD ('1'), for the construction of a static-operation CMOS type ROM. |
