发明名称 DIGITAL SIGNAL PROCESSOR
摘要 PURPOSE:To execute a complex signal processing efficiently by the small number of instructions by supplying a compared output obtained from a comparator to a microprocessor to control respectively memories. CONSTITUTION:A comparator 17 compares an output M from a multiplexer 14 with an added output N from an adder 18, and when M<N, inputs the compared output '1' to an exclusive OR (EXOR) circuit 28. The output of the EXOR circuit 28 is supplied to the switching control terminals of multiplexers 12, 19 and a latch circuit 29. The output of the EXOR circuit 28 is '1' when a flag F2 is '0' and M<N is formed, i.e. when the added output exceeds the value of an end address EA at the time of increment, and when the flat F2 is '1' and the compared output is '0', i.e. when the added output is less than the value of a start address SA at the time of decrement (M>N).
申请公布号 JPS61289440(A) 申请公布日期 1986.12.19
申请号 JP19850130842 申请日期 1985.06.18
申请人 SONY CORP 发明人 IMURA SHIGERU
分类号 G06F12/02;G06F12/00;G06F17/17;G10H1/00;H03G3/00;H03G3/02 主分类号 G06F12/02
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