| 摘要 |
PURPOSE:To improve the processing capacity of the titled device by controlling the processing so as to prevent data newly block loaded in each block from a main memory device during the invalidating processing of tag registeration from unnecessary operation due to the succeeding scalar loading instruction or tag registration invalidating request. CONSTITUTION:When the succeeding scalar data loading request or tag registration unvalidating request is inputted, the contents of a buffer updating address register 505 is compared with a block address by a comparator 507, and when the coincidence is detected by the comparator 507, a signal on a signal line 119 is turned to '0' so as to suppress an intra-area detecting signal against said scalar data loading request even if the intra-area detecting signal is sent from a signal line 703 to suppress the generation of a buffer mishit. Against the tag registration invalidating processing request, a suppress signal is sent to a buffer timing control part 503 through a signal line so as to suppress the tag registration invalidating processing of an address concerned. |
