发明名称 TIME DIVISION SWITCH CONTROL SYSTEM
摘要 PURPOSE:To prevent erroneous cutting of a semi-fixed channel by storing key information at each address in a control memory, collating it with state information included in the write indication of the control memory, which is transmitted from a central processing unit, and controlling the write validity of the control memory. CONSTITUTION:In addition to the control memory address (a) and the channel memory address (b) set to the control memory 12, a state information setting means 22 inputting a state information (s) showing the control state of the central processing unit 2 is installed in the central processing unit 2. Moreover a collating means 17 collating the state information (s) inputted from the central processing unit 2 with a state information (s') preset at the control memory address (a) in the control memory 12 is installed on a time division switch 1. According to the collation result by the collating means 17, the channel memory address (b) inputted from the central processing unit 2 and writing the state information (s) in the control memory 12 are controlled. Namely, writing at the address corresponding to the semi-fixed channel of the control memory can be prevented in a normal call processing state, and the erroneous cutting of the semi-fixed channel by the central processing unit in states other than an initialization state can be prevented.
申请公布号 JPS61289795(A) 申请公布日期 1986.12.19
申请号 JP19850132520 申请日期 1985.06.18
申请人 FUJITSU LTD 发明人 TSUBOI YOJI
分类号 H04Q3/52;H04Q11/04 主分类号 H04Q3/52
代理机构 代理人
主权项
地址