| 摘要 |
PURPOSE:To attain circuit integration of an error correcting device by constituting an interleave address generating circuit with combination of gates. CONSTITUTION:The interleave address generating circuit 85 consists of a binary counter 11, a step-up counter 12 comprising combinations of gates, a full adder 13 adding outputs of both the counters 11, 12 and a latch 14. An error correction device 8 stores temporily a consecutive data sent via a data bus 81 in a RAM83. Then a data is read from the RAM83 to an error detection correction circuit 84 by using an address generated from the circuit 85 and sent to the RAM83 via an address bus 82 so as to access the RAM83 in the order suitable for the correction. The data corrected in the error detection correction circuit 84 is written again the RAM83. After all the processings above are applied to all data in the RAM83, the data is sent again in the signal processing circuit 7, from which the data is outputted to a computer.
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