| 摘要 |
PURPOSE:To prevent a through-current from flowing to an inverter by providing an N-channel FET or a P-channel FET to one power supply of a high gain inverter of a switch comprator. CONSTITUTION:N-channel FETs 6, 7 are added respectively to inverters 2, 3. A clock phi is inputted to a gate of the N-channel FET 7. When the clock phiis at high level, the FET 7 is turned on, the inverter 3 is operated to generate a threshold value VB. The threshold value VB is inputted to the inverter 2, since the FET 6 is turned off, no through-current flows. Moreover, the threshold value VB is impressed to a gate of a P-channel FET 2a of the inverter 2 and the FET 2a is turned on and the output of the inverter 2 is fixed to the high level. Thus, the logic of the inverter 5 is fixed and no through-current flows. When the clock phi is at a low level, the FET 6 is turned on and the inverter 2 is operated. On the other hand, the FET 7 is turned off to prevent through- current of the inverter 3.
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