| 摘要 |
PURPOSE:To realize the tap delay of digital filter by reading sequentially a data from addresses A+1-A+N depending on the content A of an address register advanced sequentially and an address A+N added by a tap number N. CONSTITUTION:The content of an address register 2, a value adding a tap number N of a filter to said content are used as a write address to write the same input data to a random access memory 1, the value adding 1-N to the content of the address register 2 is used as a read address to read sequentially the data from the random access memory 1 and the multiplication and accumula tion of factors are operated by an arithmetic section 4. Cyclic advance control of 0-(N-1) is applied sequentially to the content of the address register 2 and 1-N are preset numbers, then the tap delay is realized by simple address control.
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