| 摘要 |
PURPOSE:To improve the throughput by shortening the delay time of a hold signal generating circuit in each state in the pipeline control to reduce the clock cycle of an information processor. CONSTITUTION:An instruction sent through an instruction register 31 is transmitted to stages D, A1, D2, and E and is processed in the cycle of a maximum of one clock. In case of a load/store instruction, an operation code OP and an address are sent to a buffer memory unit in the stage E. In case of an arithmetic instruction, the operation code OP and the first and the second operands Y and Z are sent to an arithmetic unit corresponding to the classification of operation in the stage following the stage E. During this period, a general register (GR) used for address generation of the load/store instruction is read out in the stage D and a GR of an arithmetic operand is read out in the stage E.
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