发明名称 SYNCHRONOUS SEPARATION CIRCUIT
摘要 PURPOSE:To separate correctly a vertical synchronizing signal from a disturbed composite synchronizing signal by sampling a composite synchronizing signal and counting a clock in response to the obtained sampling data. CONSTITUTION:An up/down counter 7 applies up-count when a composite syn chronizing signal (a) is at a high level ('H'), and applies down-count when at a low level ('L'). Thus, up-count is applied during the horizontal and vertical synchronizing periods and down-count is applied between the signals. The up- count mode and the down-count mode of the counter are decided depending on the 'H' and 'L' level of the composite synchronizing signal and the clock frequency is switched depending on the up-count mode and the down-count mode so as to detect a vertical synchronizing signal by digital processing.
申请公布号 JPS61288574(A) 申请公布日期 1986.12.18
申请号 JP19850129808 申请日期 1985.06.17
申请人 HITACHI LTD 发明人 SEKIYA MASATAKA;NISHIJIMA HIDEO;OKAMOTO CHIKAYUKI
分类号 H04N5/10 主分类号 H04N5/10
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