发明名称 PREVENTING CIRCUIT FOR DOUBLE DEPRESSION OF KEY MATRIX
摘要 PURPOSE:To prevent misencoded data from being outputted to the external by disabling the output of each priority encoder by the detection signal of an analog comparator which detects double depression of keys. CONSTITUTION:When a key of a key matrix 1 where plural keys k11-k13 are connected in a matrix is depressed, a data signal having a code constitution different from that of the data signal applied from each row signal line 3 to each row signal line 2 is outputted, and row signal lines 3 are scanned to take in the state of keys. The base of a transistor TR is connected to each column signal line 3, and each row signal line 2 is grounded through a resistance Rd. Priority encoders 4 and 5 are connected to row and column outputs, and the output of a comparator 6 is applied to their control terminals G. Thus, misencoded data is prevented from being outputted from priority encoders 4 and 5 to the external.
申请公布号 JPS61288219(A) 申请公布日期 1986.12.18
申请号 JP19850129397 申请日期 1985.06.14
申请人 YOKOGAWA ELECTRIC CORP 发明人 UDA KENJI;KOGA IZUMI
分类号 G06F3/02 主分类号 G06F3/02
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