| 摘要 |
PURPOSE:To store a video in a video region in a memory without fail even when the pulse width is fluctuated while a delay time of a video signal of an ITV camera is neglected by generating a memory address signal and a memory write signal from the leading of a blank signal. CONSTITUTION:A blank signal (c) is extracted from a composite video signal (j) by a blank signal extraction circuit 6 and given to a memory timing genera tor 2. The memory timing generator 2 generates the memory address signal (g) and the memory write signal (h) from the leading of the blank signal (c) to form a memory fetch effective area M2. Further, a shift clock signal (e) and a load signal (f) are generated and given to a serial input/parallel output shift register 4. Since they are extracted from the composite video signal (j), no delay time is caused. Thus, the video fetch region V2 in the composite video signal (j) is coincident with the memory fetch effective region M2 without fail and the full video region is stored in memory 5.
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