发明名称 DATA BUFFERING CONTROLLER
摘要 PURPOSE:To increase the transmission speed of a transmission line by using the count output of a difference between the write number of times and the read number of times of data to a reception data buffer so as to correct the data read frequency according to the change in the shortage quantity. CONSTITUTION:A voice data 1A from a transmission side is outputted as a data 1B from an address deciding circuit 2 and stored in a reception data buffer 8 in the timing by a write signal made by a reception clock recovery circuit 3. Then the data is read from the butter 8 by using a signal being the correction result of a read signal formed by a sampling control circuit 9 by a frequency control circuit 6 and sent to a receiver 5. The read signal from the circuit 3 is added by a counter 7 and the read signal from the circuit 6 is inputted as a subtraction signal to the counter 7. Then the timing of the read signal of the circuit 6 is controlled by the output of the counter 7 to keep the storage quantity of the buffer 8 to a constant quantity.
申请公布号 JPS61288644(A) 申请公布日期 1986.12.18
申请号 JP19850129944 申请日期 1985.06.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 YAMAGUCHI FUMITOSHI;ENAMI YOSHITAKA
分类号 H04L13/08;G06F5/06 主分类号 H04L13/08
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